1. Field of the Invention
This invention relates to integrated circuit manufacturing and, more particularly, to a substantially planarized interconnect topography and method for making substantially planarized electrically conductive features such as wide interconnect structures by fabricating the electrically conductive features around a plurality of posts.
2. Description of the Related Art
Fabrication of an integrated circuit involves numerous processing steps. After implant regions (e.g., source/drain regions) have been placed within a semiconductor substrate and gate areas defined upon the substrate, an interlevel dielectric is formed across the topography to isolate the gate areas and the implant regions from overlying conducting regions. Interconnect routing is then patterned across the interlevel dielectric and connected to the implant regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric. Alternating levels of interlevel dielectric and interconnect may be placed across the semiconductor topography to form a multi-level integrated circuit.
As successive layers are deposited across previously patterned layers of an integrated circuit, elevational disparities develop across the surface of each layer. If left unattended, the elevational disparities in each level of an integrated circuit can lead to various problems. For example, when a dielectric, conductive, or semiconductive material is deposited over a topological surface having elevationally raised and recessed regions, step coverage problems may arise. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Also, stringers may arise from incomplete etching over severe steps. Furthermore, correctly patterning layers upon a topological surface containing fluctuations in elevation may be difficult using optical lithography. The depth-of-focus of the lithography alignment system may vary depending upon whether the resist resides in an elevational xe2x80x9chillxe2x80x9d or xe2x80x9cvalleyxe2x80x9d area. The presence of such elevational disparities therefore makes it difficult to print high-resolution features.
Techniques involving chemical and mechanical abrasion (e.g., chemical-mechanical polishing) to planarize or remove the surface irregularities have grown in popularity. As shown in FIG. 1, a typical chemical-mechanical polishing (xe2x80x9cCMPxe2x80x9d) process involves placing a semiconductor wafer 12 face-down on a polishing pad 14 which lies on or is attached to a rotatable table or platen 16. A popular polishing pad medium includes polyurethane or polyurethane-impregnated polyester felts. During the CMP process, polishing pad 14 and semiconductor wafer 12 may be rotated while a carrier 10 holding wafer 12 applies a downward force F upon polishing pad 14. An abrasive, fluid-based chemical suspension, often referred to as a xe2x80x9cslurryxe2x80x9d, may be deposited from a conduit 18 positioned above pad 14 onto the surface of polishing pad 14. The slurry may fill the space between pad 14 and the surface of wafer 12. The polishing process may involve a chemical in the slurry reacting with the surface material being polished. The rotational movement of polishing pad 14 relative to wafer 12 preferably causes abrasive particles entrained within the slurry to physically strip the reacted surface material from wafer 12. The pad 14 itself may also physically remove some material from the surface of the wafer 12. The abrasive slurry particles are typically composed of silica, alumina, or ceria.
CMP is commonly used to form a planarized level of an integrated circuit containing interconnect laterally spaced from each other in what is generally referred to as the xe2x80x9cdamascenexe2x80x9d process. Laterally spaced trenches are first etched in an interlevel dielectric configured upon a semiconductor topography comprising electrically conductive features. A conductive material is then deposited into the trenches and on the interlevel dielectric between trenches to a level spaced above the upper surface of the interlevel dielectric. CMP is applied to the surface of the conductive material to remove that surface to a level substantially commensurate with that of the upper surface of the interlevel dielectric. In this manner, interconnects that are isolated from each other by the interlevel dielectric are formed exclusively in the trenches. CMP can planarize only localized regions of the interconnect surface such that all interconnect traces have a co-planar upper surface, provided certain conditions are met. The localized area must contain trenches that are consistently and closely spaced from each other. Moreover, the trenches must be relatively narrow in lateral dimension. If those rather restrictive requirements are not met, then thicknesses of a given interconnect layer can vary to such a degree that local regions of interconnect may suffer severe current-carrying limitations.
In particular, planarization may become quite difficult in a region where there is a relatively large distance between a series of relatively narrow interconnect, or if there is a relatively wide interconnect such as that found in, for example, a bond pad or a wide conductive line, such as a bus. FIGS. 2-5 illustrate a typical damascene process and the localized thinning or xe2x80x9cdishingxe2x80x9d problem experienced by conventional metal CMP processes when a relatively wide interconnect is planarized.
FIG. 2 depicts a partial top view of a bond pad 22, possibly up to or exceeding 100 xcexcm per side, formed in an interlevel dielectric 20 according to a conventional process. FIG. 3 shows a partial cross-sectional view of the semiconductor topography including the bond pad along line A. A relatively wide trench 24 is formed in interlevel dielectric 20 using well-known lithography and etch techniques. FIG. 4 illustrates a conductive material 28, e.g., a metal, such as aluminum, tungsten, tantalum, or titanium, deposited across the topography to a level spaced above upper surface 26. Due to the conformal nature of the sputter or CVD process used to apply the conductive material, the conductive material takes on an upper surface topography including a region 30 having a single wide valley area spaced above the wide trench 24 and a substantially flat region 32 spaced above smooth upper surface 26. Conductive material 28 is then polished, as shown in FIG. 5, using CMP to remove conductive material 28 from the upper surface of interlevel dielectric 20. As a result of CMP, a relatively wide interconnect 34 is formed exclusively in wide trench 24. As shown in FIG. 5, the wide interconnect 34 may subsequently function as a bond pad. A similar process may be used to form other wide interconnects, such as buses or other wide conductive lines.
Unfortunately, the topological surface of the interconnect level is not absent of elevational disparity. That is, the upper surface of interconnect 34 includes a recessed area 36 that extends below a substantially planar upper surface 38 of interlevel dielectric 20. Recessed area 36 may result from a phenomenon known as the xe2x80x9cdishingxe2x80x9d effect. Dishing naturally results from the polishing pad flexing or conforming to the surface being polished. If the surface being polished is initially bowed or arcuate (i.e., is not planar), the polishing pad will take on the shape of the non-planar regions causing further dishing of the surface being polished. The CMP slurry initiates the polishing process by chemically reacting with the surface material in both elevated and recessed areas. Because of the deformation of the CMP pad, the reacted surface material in recessed areas may be physically stripped in addition to the reacted surface material in elevated areas. As such, a surface having fluctuations in elevation may continue to have some elevational disparity even after it has been subjected to CMP. The dishing effect is particularly a problem when forming a relatively wide interconnect between regions of a dielectric that is substantially more dense than the metal. While the dielectric is hard enough to support the overlying regions of the CMP pad, the metal is not, and thus allows significant flexing of the pad. Such flexing of the CMP pad may cause the surface of the metal interconnect to become recessed relative to adjacent regions of the dielectric.
It would therefore be desirable to develop a polishing process which can achieve global planarization across the entire topological surface of an interconnect level. Global planarization requires that the polish rate be uniform in all elevated areas of the topography. Such uniformity of the polish rate is particularly needed when polishing a topography having a relatively wide interconnect, a wide interconnect interspersed with other wide interconnects, or a wide interconnect interspersed with densely spaced or sparsely spaced narrow (or xe2x80x9csmallxe2x80x9d) interconnects. The desired polishing process must avoid problems typically arising during CMP of varying metal substrate area, such as metal dishing.
The problems outlined above are in large part solved by an embodiment of the present invention in which a substantially planar semiconductor topography is fabricated by forming a plurality of posts in a dielectric layer in a region defined by a relatively wide interconnect. The dielectric layer may include a material having a relatively low dielectric constant such as a glass- or silicate-based dielectric, preferably silicon dioxide.
According to an embodiment, trenches are first etched in the dielectric layer to form a plurality of posts surrounded by the trenches. The widths, lengths, and depths of the trenches and the widths of the posts may vary according to design preferences and criteria. In an embodiment in which a bond pad is to be formed, both the trenches and the posts may have widths of about 10 xcexcm. In an alternative embodiment, the trenches may have a width of about 9 xcexcm and the posts may have a width of about 1 xcexcm. The overall length (lateral dimension) of the etched area is preferably between about 75 xcexcm and about 100 xcexcm. The depth of the trenches is preferably greater than about 0.2 xcexcm. According to an embodiment in which a wide conductive line such as, e.g., a power or ground conductor within a bus is to be formed, the conductive line may have a width of at least about 5 xcexcm and the posts may have a width of at least about 1 xcexcm. The depth of the trenches is preferably greater than about 0.2 xcexcm.
The trenches are filled with a conductive material, e.g., a metal or an alloy of a metal such as aluminum, copper, tungsten, molybdenum, tantalum, or titanium. The conductive material is preferably deposited to a level spaced above the upper surface of the dielectric layer. The surface of the conductive material is then polished to a level substantially coplanar with the level of the upper surfaces of the dielectric layer and the posts. Advantageously, the polish rate of the conductive material above the trenches and the posts is substantially uniform. The posts preferably serve to improve the planarization of the conductive material surrounding them.
In one embodiment, the conductive material may be polished using well-known CMP. That is, the front side of the semiconductor topography may be forced against a CMP polishing pad while the polishing pad and the topography are rotated relative to each other. A CMP slurry entrained with abrasive particles, e.g., ceria, silica, or alumina, may be dispensed upon the polishing pad surface to aid in the removal of the conductive material. In an alternate embodiment, a xe2x80x9cfixed-abrasivexe2x80x9d technique may be used to polish the conductive material. The fixed-abrasive technique involves placing a liquid that is substantially free of particulate matter between the surface of the conductive material and an abrasive polishing surface of a polishing pad. The fixed abrasive technique avoids liquids that contain chemical constituents that could react with the topography. The abrasive polishing surface is moved relative to the semiconductor topography so as to polish the conductive material. The liquid applied to the polishing surface preferably comprises deionized water, however, other liquids which have a near-neutral pH value may alternatively be directed onto the fixed abrasive polishing surface. The pH that is chosen for the polishing process is one suitable for the conductive material and the polishing pad. The polishing surface may include a polymer-based matrix entrained with particles selected from the group consisting of cerium oxide, cerium dioxide, aluminum oxide, silicon dioxide, titanium oxide, chromium oxide, and zirconium oxide.
The abrasive polishing surface preferably belongs to a polishing pad which is substantially resistant to deformation even when placed across an elevationally recessed region of relatively large lateral dimension (e.g., over 200 xcexcm lateral dimension). Therefore, the pad is preferably relatively non-conformal to the underlying surface and thus does not come in contact with elevationally recessed regions of the conductive material. It is believed that particles dispersed throughout the abrasive polishing surface in combination with the polishing liquid interact chemically and physically with elevated regions of the conductive material to remove those regions. However, the liquid alone may be incapable of removing the conductive material in elevationally recessed regions. As such, elevationally raised regions of the conductive material may be removed at a substantially faster rate than elevationally recessed regions. The polish rate preferably slows down significantly as the topological surface of the interconnect level approaches planarity.
Whatever polishing technique is applied to the conductive material, the presence of the posts within the conductive material preferably provides for global planarization of the topography employing the posts. It is theorized that the dielectric material of the posts, being denser than the conductive material, causes the polishing pad to remain substantially flat when pressure is applied thereto. That is, the surface area of the dielectric protrusions within the conductive material is not sufficient to withstand the force of the polishing pad, and thus does not cause the pad to flex. Therefore, dishing of the conductive material in the large area metal-filled trenches (e.g., bond pads greater than about 75 xcexcm per side or interconnects greater than about 5 xcexcm wide) is less likely to occur as a result of the polishing process.
The conductive material may continue to be polished more rapidly than the dielectric once the surface of the conductive material has been removed to the same elevational plane as the dielectric. The dielectric protrusions within the conductive material may thus become elevated above the conductive material. Consequently, the entire topological surface of the bond pad may have surface disparities, causing the polish rate of the elevated dielectric protrusions to become greater than that of the recessed conductive material. As the polishing process continues, the dielectric protrusions are again made substantially coplanar with the conductive material. This cycle may be repeated until it is desirable to stop the polishing process.